ESD (Electrostatic Discharge) protection design is a major factor in the reliability of deep-submicron CMOS Integrated Circuits (ICs). Since CMOS development technology is aggressive in the deep-submicron category, the device size and the thickness of the gate oxide are being continually reduced to improve the operating speed of the CMOS devices and integration density of the ICs. These highly scaled-down devices, however, have been found to be increasingly vulnerable to ESD. Therefore, ESD protection circuits have been added into the CMOS IC's to protect the IC's against ESD damage.
As a result of detailed investigations of ESD events on IC products, it is known that there are three main types of ESD events: Human-Body Model (HBM), Machine Model (MM), and Charge Device Model (CDM). These three ESD models have been well understood, and have been widely used as the industrial ESD testing standards.
A high potential may be generated on an input or output buffer of the integrated circuit. When the electrostatic charges are discharged, a high current is produced at the package nodes of the integrated circuit, and is referred to as electrostatic discharge (ESD).
Due to the continuing trend towards miniaturization of electronic devices, smaller critical dimensions and thinner dielectric layers are being used, which are more prone to damage from ESD events. It is therefore desirable to have improvements in the protection circuits used for preventing damage due to ESD.